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Altera_Forum
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11 years ago

Cyclone V Altera PLL Can't do 100 MHz.

Hello, I am desiging a custom board based on the Altera Cyclone V board. I've changed the board oscillator from 50 MHz to 100 MHz. I am trying to make it go throught a PLL inside QSys and then feed 1...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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It could be but when I take out the DMA of the Bridge I have no timing problems, All I have in this bridge (FPGA2SDRAM) is a TSE MAC and a DMA and that's pretty much my whole design...

If the timing report says this FMAX is 91.73 MHz I don't have much to misunderstand, do I?

Thanks

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I think you have timing constraint problem.

- check .sdc file for the clock signal and add a proper timing constraint

It is not a Altera PLL IP problem (you can check it in Qsys GUI, that all clocks compensated. It it has a problem that means 99.9 Mhz instead of 100 MHz).

I suggest to examine the following good documentation.

http://www.alterawiki.com/wiki/timequest_user_guide