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Altera_Forum
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11 years ago

Cyclone V Altera PLL Can't do 100 MHz.

Hello, I am desiging a custom board based on the Altera Cyclone V board. I've changed the board oscillator from 50 MHz to 100 MHz. I am trying to make it go throught a PLL inside QSys and then feed 1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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I know it's not a PLL per se problem, I think I really made the wrong question. I would like to know the the FPGA2SDRAM / FPGA2HPS LW bridges can run at 100MHz;

I get the top falling path from the SOC System LW Bridge to the HPS System with a slack of -0.4

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I have tested all bridges (H2F, F2H, H2F_LW). They can work ~ 100 / 133 / 166 MHz clock frequencies.

I have no information about the FPGA2SDRAM interfaces. (note. this is a interface, not a bridge).