Cyclone III max I/O frequency

(I'm guessing that you are driving at 1.8V levels on a dedicated clock output).

Have a look at :

"Maximum Output Toggle Rate on Cyclone III Devices (MHz)"

in here:

http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf (http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf)

You may have to use a higher speed grade.

Thank you all for the good information.

I´m using SSTL2 on bank 8 of the FPGA (pin B6). Speedgrade -8 Comercial type.

This is a row I/O pin isn´t it?

Looking at page 30 on the pdf I can see that the toggle frequency should be 280Mhz.

Quartus told me tha only 210Mhz are possible!

How could that be?

what is the derating factor on page 33?

regards

Cyclone

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what is the derating factor on page 33?

Cyclone

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See calculations on p28. It's to account for the effects of specified output pin load capacitance (which you also need to account for if you want to get an accurate timing model).

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See calculations on p28. It's to account for the effects of specified output pin load capacitance (which you also need to account for if you want to get an accurate timing model).

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OK.

That shouldnt be the problem in my case because there is 0pF load specified in quartus.

Due to this the max. frequency should be 280Mhz and not 210Mhz?:confused: :confused:

I also tried speedgrad 6 and 7 and there is no problem :(

There are a number of possibilities:

1) You haven't set SSTL_2 as you thought (double check)

2) The timing model in Quartus may not be up to date with the latest product information (check with Altera)

3) Something else we both don't understand (quite possible, contact Altera via your distributor or directly via the web-site support I would suggest)

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There are a number of possibilities:

1) You haven't set SSTL_2 as you thought (double check)

2) The timing model in Quartus may not be up to date with the latest product information (check with Altera)

3) Something else we both don't understand (quite possible, contact Altera via your distributor or directly via the web-site support I would suggest)

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1) I have checked it again and the pin is set to SSTL2-CLASS I

2) I also thought about that and I hope that that is my problem :D

3) I also started a request to altera but I found out that the information in this forum (as you could see in this threat) is faster and there are also quiet good ideas!

THANK you all

:rolleyes:

To address your previous question on whether B6 in bank 8 is a column or row pin. Bank 8 is on the top left and from the I/O bank diagram in the pin table on page 14 it is shown as a column pin.

http://www.altera.com/literature/dp/cyclone3/ep3c25.pdf

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To address your previous question on whether B6 in bank 8 is a column or row pin. Bank 8 is on the top left and from the I/O bank diagram in the pin table on page 14 it is shown as a column pin.

http://www.altera.com/literature/dp/cyclone3/ep3c25.pdf

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hmmm... is that name convention because of row and column LE interconnection within the FPGA :confused: ?