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Altera_Forum
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18 years ago

Cyclone III max I/O frequency

Hi, I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In q...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

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See calculations on p28. It's to account for the effects of specified output pin load capacitance (which you also need to account for if you want to get an accurate timing model).

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OK.

That shouldnt be the problem in my case because there is 0pF load specified in quartus.

Due to this the max. frequency should be 280Mhz and not 210Mhz?:confused: :confused:

I also tried speedgrad 6 and 7 and there is no problem :(