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Honored Contributor
Honored ContributorCyclone III max I/O frequency
Hi, I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In q...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- To address your previous question on whether B6 in bank 8 is a column or row pin. Bank 8 is on the top left and from the I/O bank diagram in the pin table on page 14 it is shown as a column pin. http://www.altera.com/literature/dp/cyclone3/ep3c25.pdf --- Quote End --- hmmm... is that name convention because of row and column LE interconnection within the FPGA :confused: ?
