Altera_ForumHonored Contributor18 years agoCyclone III max I/O frequency Hi, I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In q...Show More
Altera_ForumHonored Contributor18 years agoYes. Column pins connect to column interconnect. Row pins connect to row internconnect.
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