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Altera_Forum
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18 years ago

Cyclone III max I/O frequency

Hi, I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In q...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Thank you all for the good information.

I´m using SSTL2 on bank 8 of the FPGA (pin B6). Speedgrade -8 Comercial type.

This is a row I/O pin isn´t it?

Looking at page 30 on the pdf I can see that the toggle frequency should be 280Mhz.

Quartus told me tha only 210Mhz are possible!

How could that be?

what is the derating factor on page 33?

regards

Cyclone