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Honored Contributor
Honored ContributorCyclone III max I/O frequency
Hi, I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In q...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- what is the derating factor on page 33? Cyclone --- Quote End --- See calculations on p28. It's to account for the effects of specified output pin load capacitance (which you also need to account for if you want to get an accurate timing model).
