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Altera_Forum
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18 years ago

Cyclone III max I/O frequency

Hi, I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In q...
Altera_Forum's avatar
Altera_Forum
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18 years ago

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what is the derating factor on page 33?

Cyclone

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See calculations on p28. It's to account for the effects of specified output pin load capacitance (which you also need to account for if you want to get an accurate timing model).