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Altera_Forum's avatar
Altera_Forum
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19 years ago

Cyclone III max I/O frequency

Hi, I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In q...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

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There are a number of possibilities:

1) You haven't set SSTL_2 as you thought (double check)

2) The timing model in Quartus may not be up to date with the latest product information (check with Altera)

3) Something else we both don't understand (quite possible, contact Altera via your distributor or directly via the web-site support I would suggest)

--- Quote End ---

1) I have checked it again and the pin is set to SSTL2-CLASS I

2) I also thought about that and I hope that that is my problem :D

3) I also started a request to altera but I found out that the information in this forum (as you could see in this threat) is faster and there are also quiet good ideas!

THANK you all

:rolleyes: