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Altera_Forum
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18 years ago

Cyclone III max I/O frequency

Hi, I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In q...
Altera_Forum's avatar
Altera_Forum
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18 years ago

There are a number of possibilities:

1) You haven't set SSTL_2 as you thought (double check)

2) The timing model in Quartus may not be up to date with the latest product information (check with Altera)

3) Something else we both don't understand (quite possible, contact Altera via your distributor or directly via the web-site support I would suggest)