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Altera_Forum
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18 years ago

Cyclone III max I/O frequency

Hi, I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In q...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Looking at the table in the PDF noted above you'll have to know whether it is a row, column, or dedicated pin like a PLL output pin. Also, which SSTL2 Class.