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Honored Contributor
Honored ContributorCyclone III max I/O frequency
Hi, I´m using a PLL to generate a 250Mhz clock with a phase shift of 2,7ns on a CylconeIII EP3C25(-8) I want to provide this clock on a pll output pin with SSTL 2,5V standard. In q...
Altera_ForumHonored Contributor
Honored ContributorLooking at the table in the PDF noted above you'll have to know whether it is a row, column, or dedicated pin like a PLL output pin. Also, which SSTL2 Class.
