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Honored ContributorBeMicro UART Interface no data on RxD
Hi @ all
I tried the following vhdl process code in order to receive data from pc com interface: com: process (clk) variable temp : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000"; variable zaehler : integer := 100; variable modus : bit := '0'; begin -- all led off if zaehler = 100 then led0 <= '1'; led1 <= '1'; led2 <= '1'; led3 <= '1'; led4 <= '1'; led5 <= '1'; led6 <= '1'; led7 <= '1'; zaehler := 99; end if; if modus = '0' then ------------------------------------------------------------------ if rxd = '1' then modus := '1'; zaehler := 0; led1 <= '0'; end if; ------------------------------------------------------------------ -- rxd does not receive data -- pin planner rxd = PIN_C8 ------------------------------------------------------------------ else end if; end process com; the led1 does not turn on as i would expect when sending data via com interface? do you have an clue what i am doin wrong. I believe that the data that is sent by the pc is not reaching the rxd pin? best regards thomas9 Replies
Altera_ForumIt should work, if the serial port is already configured correctly (baud rate, parity, number of bits...)
You can aslo use a terminal (such as termite (http://www.compuphase.com/software_termite.htm), just avoid Hyperterminal), it should make it easier.- Altera_Forum
I did add the if rising_edge command into the code and know it receives something. I saved a ascii.txt file with an a and used "copy ascii.txt com5:" in order to send the "a" to the fpga.
Do you know if the plain "a" arrives at the stick if i use the copy command as a test? Edit: I only have an Rx signal but no other control signals. - Altera_Forum
perhaps VHDL-2008 and its process(all) addition will help this misconception. then in teaching advanced simulation you could introduce adding/removing signals from the process statement
- Altera_Forum--- Quote Start --- Hi I thought The process itself is clk sensitive, every Time The clk Signal changes The Process gets executed. In your Code example it is just rising Edge sensitive or is there something Else that i Miss at that Point? --- Quote End --- The synthesizer ignores the process sensitivity list. You need to explicitly put an edge-sensitive 'if' to make it a clocked process.
- Altera_Forum--- Quote Start --- I thought The process itself is clk sensitive, every Time The clk Signal changes The Process gets executed. --- Quote End --- It's common misunderstanding in VHDL design. It possibly works in simulation but never in synthesized logic (FPGA hardware). VHDL is a hardware description language, not a procedural programming language that is executed sequentially. Examine existing UART designs. They performing everything in an edge sensitive process block. P.S.: Regarding rxd polarity, I really meant "in addition". Without a reasonable edge sensitive process trigger, it can't work either.
- Altera_Forum
Hi
I tried the if Statement with rxd ='1' and with rxd='0' but in both Cases i got always nö Response (LED). - Altera_Forum--- Quote Start --- you should put all the contents of your process inside a
loop to be sure that everything is clocked. --- Quote End --- Hi I thought The process itself is clk sensitive, every Time The clk Signal changes The Process gets executed. In your Code example it is just rising Edge sensitive or is there something Else that i Miss at that Point?if rising_edge(clk) ... end if - Altera_Forum
In addition, did you notice, that a (logic level) UART has an idle state of '1' and a start bit of '0'?
You could start with a proven UART code, some can be found in Altera forum's previous discussions. - Altera_Forum
you should put all the contents of your process inside a
loop to be sure that everything is clocked.if rising_edge(clk) ... end if
