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I thought The process itself is clk sensitive, every Time The clk Signal changes The Process gets executed.
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It's common misunderstanding in VHDL design. It possibly works in simulation but never in synthesized logic (FPGA hardware). VHDL is a hardware description language, not a procedural programming language that is executed sequentially.
Examine existing UART designs. They performing everything in an edge sensitive process block.
P.S.: Regarding rxd polarity, I really meant "in addition". Without a reasonable edge sensitive process trigger, it can't work either.
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