Forum Discussion
Altera_Forum
Honored Contributor
16 years agoBeMicro UART Interface no data on RxD
Hi @ all I tried the following vhdl process code in order to receive data from pc com interface: com: process (clk) variable temp : std_logic_vector(47 downto 0) := "0000000000000000000...
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- you should put all the contents of your process inside a
if rising_edge(clk)
...
end ifloop to be sure that everything is clocked. --- Quote End --- Hi I thought The process itself is clk sensitive, every Time The clk Signal changes The Process gets executed. In your Code example it is just rising Edge sensitive or is there something Else that i Miss at that Point?