beginners question: MAX V capacity needed for simple glue logic

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Hello,

I am looking for a simple glue logic solution.

2 image sensors will simultaneously output 8-bit image data at a rate of 25Mhz. I want to import this into a microcontroller as 8 bit data at a rate of 50Mhz. The glue logic will have to take the 2 bytes in parallel and then output them one after the other to the microcontroller.

I thought a MAX V device might work well in this application. I am just not sure how much can be done with one of those logic cells. For example,

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if I were to do it in a 5M40, would it fit?

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Your limiting factor here, is how many registers you need. So at a minimum you need 16 registers, so this should fit.. The key question are all the clocks related. IE are they syncronous or asyncronous to each other?

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And if so, would there be spare resources left?

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Yes you should have some spare resources, if the clocks are syncrounous.

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What if I would include a FIFO of a few byte? How well can this be done?

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The MaxV doesn't have any ram in the fabric, so any fifo would eat logic elements. You basically need an LE for each register. So at max you would be able to do a two stage ping-pong (32 registers) in the 5M40. Not much space. But if you have async clocks your are going to need more to take care of the metastability issues properly.

In that case I would sugest the next device up.

If you need deep fifos, I suggest you look at a small FPGA.

Pete

To decide if 5M40 can do the job, you'll write the code and compile it.

Your description isn't really informative about the possible role of a FIFO. If your glue logic needs to handle asynchronicity of data streams, I guess it won't fit into 32 LEs.

By the way, which microcontroller can achieve 50 MByte/s continuous data rate? Or is it only DMA based single frame grabbing?

Thanks for your quick response.

The clocks are more or less synchronized. The sensors are running from the same clock, but this clock is an oscillator. I found that the signal does not have steep edges. As a result there will be a different skew for each sensor. I might just buffer the clock. That will probably solve this.

I was looking for (relatively) simple programmable logic. This could be either a small FPGA or CPLD. What I like about MAX V is the fact that it does not need external memory and that it is really low cost. There is some other functionalities that I want to build in other applications. However, these would use more registers. Now I am thinking: what else can I do with the MAX V? Would it be feasible?

I would need some 8 to 10-bit counters and adders. This will definitely not work on a 5M40, but maybe one of the larger models.

Can I safely assume that the registers are also the limiting factor here? I mean, if I were to implement a 10-bit counter, would I need 10 LEs then, or could it need more? What about an 8 bit adder? I know I am pushing it now, but it might just work...

I have decided to not use a FIFO. I guess I will need the following:

- use a 50Mhz master clock. To the sensors this will be a half clock.

- divide by 2 and use as main clock for the sensors

-For each sensor: latch the data on the rising edge of the pixel clock (which is almost the same as the sensors main clock)

- Clock out the 1st sensors data on the 1st half-clock cycle after reception of the data

- clock out the 2ns sensors data on the 2nd half-clock cycle

I think you can call this pretty much synchronous. There might be some skew issues, but the basic phase info will be known.

Yes the MCU will mainly use DMA. The data will be transferred from the sensor to USB through a FIFO. The basic rate is a bit too fast for USB, so the data will need to be temporarily buffered. One DMA will take the image data to the RAM. The other will move from memory to USB. The sensor has blanking periods in which the FIFO can be flushed.

Fortunately we can afford to use a lower frequency for sensor clk if the MCU will not keep up.

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MAX V has LEs with 4-bit input LUT similar to Cyclone I to IV. For the mentioned functions like 10-Bit counter or 8-bit adder, you can expect 1 LE per bit. Complex logic might consume additional LEs for intermediate terms.

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And if you use ripple logic? 2 inputs, one carry in one carry out?

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And if you use ripple logic? 2 inputs, one carry in one carry out?

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That's the default adder implementation, also used for the binary counter.

It's easy to check the implementation in Quartus netlist viewer.

You have a point there.

I found that the initial problem can very well be done with a MAX V, so it is worth it to install Quartus an put it to the test.

I will go ahead and do that.