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Hello,
I am looking for a simple glue logic solution.
2 image sensors will simultaneously output 8-bit image data at a rate of 25Mhz. I want to import this into a microcontroller as 8 bit data at a rate of 50Mhz. The glue logic will have to take the 2 bytes in parallel and then output them one after the other to the microcontroller.
I thought a MAX V device might work well in this application. I am just not sure how much can be done with one of those logic cells. For example,
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if I were to do it in a 5M40, would it fit?
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Your limiting factor here, is how many registers you need. So at a minimum you need 16 registers, so this should fit.. The key question are all the clocks related. IE are they syncronous or asyncronous to each other?
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And if so, would there be spare resources left?
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Yes you should have some spare resources, if the clocks are syncrounous.
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What if I would include a FIFO of a few byte? How well can this be done?
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The MaxV doesn't have any ram in the fabric, so any fifo would eat logic elements. You basically need an LE for each register. So at max you would be able to do a two stage ping-pong (32 registers) in the 5M40. Not much space. But if you have async clocks your are going to need more to take care of the metastability issues properly.
In that case I would sugest the next device up.
If you need deep fifos, I suggest you look at a small FPGA.
Pete
Honored Contributor
