Honored Contributorhi agin,
I whant to clock in data at the rate of 48MHz (Camera). At the falling edge of the PIX_CLK data is valid. My design will work at 48MHz but the both clk's wont be synchronised. Q1: The best way to write a VHDL for this so that the data will be synchronized to the design CLK? Q2: How to add this in SDC file for a propper timing analyse?
Honored Contributor1. Stick a dual clock fifo between the 2 clock domains.
Honored ContributorBut the two domains are at the same clkfreq. Wont this be a waist of
resources? Or is the use of a small fifo not that bad ?Honored Contributorunless they are synchronised, you will have to assume each clock domain is completly seperate, and hence a fifo is required.
Honored ContributorOK Thx! Constraining is no problem then.
Only applying 2 clk domainsHonored ContributorStrictly spoken, you don't need a FIFO, just a means to transfer a data word consistenly across the clock boundary, e.g. a register pair with a handshake protocol.
In any case, (with or without a FIFO), you won't be able to receive a continous data stream at a (slightly) different clock rate. From time to time, you have to skip or to fill a sample.Honored ContributorIf both freq's are 48MHz will i miss data? Even the fifo add's
latency of 2 clk's? Edit: I wont miss data. You are talking about continuous data stream. Srry It's no problem if i don't have a continuous data stream. I use the FIFO as async. clk's and the nFIFO_EMPTY as DATA_VALID.Honored ContributorThe problem is mostly if your two clocks aren't at the same exact frequency. If they come from the same oscillator, but are shifted, then you won't miss any data. But if there is a slight frequency difference, then from time to time either one word won't get read in time (it will fill the fifo with one additional word), or the read side will attempt to read the fifo but no data will be available. If you have a 100ppm difference this will happen approximately every 0.2ms so it's not negligible.
Edit: oups, didn't see you didn't have a continuous stream... then as long as you use the fifo's full and empty signals to control the flow, you should be okHonored ContributorI don't really get how this design can work.
let me explain my doubt. The input FIFO is filled with data from the camera external clock. The internal circuit reads, let's say, the First Out bit from the FIFO. Thie read operation is synchronized on another clock domain (apporx. same frequency). It can happen that, due to frequency shift, at a certain point the second clock violate setup/hold times of the FIFO and reads a different data from what is expected. If these data are video pixels, this causes a very dangerous shift in the image. Am I wrong? What about using a PLL to synchronize the internal clock to the external clock?Honored ContributorBut the data is buffered in a DCFIFO.
I don't need a continuous data stream, but i do need the data to be complete. I have 2 camera's so i can't synchronize the internal clk to both camera's. Altho both are working on 48MHz. And the FPGA will work at 100MHz. Cauze FPGA must handle both camera's at the same time.Honored ContributorIt is well known practice in multiple video inputs to use fifos. One fifo to bridge data from camera1 to the 100MHz and the second fifo to bridge the other camera.
IN the 100MHz domain you can then time mux the data if you wish serial processing as two channels. I don't foresee any problems.
