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Altera_Forum
Honored Contributor
Honored ContributorAsynchronous data
hi agin, I whant to clock in data at the rate of 48MHz (Camera). At the falling edge of the PIX_CLK data is valid. My design will work at 48MHz but the both clk's wont be synchronised...
Altera_ForumHonored Contributor
Honored ContributorStrictly spoken, you don't need a FIFO, just a means to transfer a data word consistenly across the clock boundary, e.g. a register pair with a handshake protocol.
In any case, (with or without a FIFO), you won't be able to receive a continous data stream at a (slightly) different clock rate. From time to time, you have to skip or to fill a sample.
