Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAsynchronous data
hi agin, I whant to clock in data at the rate of 48MHz (Camera). At the falling edge of the PIX_CLK data is valid. My design will work at 48MHz but the both clk's wont be synchronised...
Altera_ForumHonored Contributor
Honored ContributorI don't really get how this design can work.
let me explain my doubt. The input FIFO is filled with data from the camera external clock. The internal circuit reads, let's say, the First Out bit from the FIFO. Thie read operation is synchronized on another clock domain (apporx. same frequency). It can happen that, due to frequency shift, at a certain point the second clock violate setup/hold times of the FIFO and reads a different data from what is expected. If these data are video pixels, this causes a very dangerous shift in the image. Am I wrong? What about using a PLL to synchronize the internal clock to the external clock?
