Honored Contributor
Honored ContributorI don't really get how this design can work.
let me explain my doubt. The input FIFO is filled with data from the camera external clock. The internal circuit reads, let's say, the First Out bit from the FIFO. Thie read operation is synchronized on another clock domain (apporx. same frequency). It can happen that, due to frequency shift, at a certain point the second clock violate setup/hold times of the FIFO and reads a different data from what is expected. If these data are video pixels, this causes a very dangerous shift in the image. Am I wrong? What about using a PLL to synchronize the internal clock to the external clock?
