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Altera_Forum's avatar
Altera_Forum
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15 years ago

Asynchronous data

hi agin, I whant to clock in data at the rate of 48MHz (Camera). At the falling edge of the PIX_CLK data is valid. My design will work at 48MHz but the both clk's wont be synchronised...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

If both freq's are 48MHz will i miss data? Even the fifo add's

latency of 2 clk's?

Edit: I wont miss data. You are talking about continuous data stream. Srry

It's no problem if i don't have a continuous data stream.

I use the FIFO as async. clk's

and the nFIFO_EMPTY as DATA_VALID.