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Altera_Forum's avatar
Altera_Forum
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15 years ago

Asynchronous data

hi agin, I whant to clock in data at the rate of 48MHz (Camera). At the falling edge of the PIX_CLK data is valid. My design will work at 48MHz but the both clk's wont be synchronised...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

But the data is buffered in a DCFIFO.

I don't need a continuous data stream,

but i do need the data to be complete.

I have 2 camera's so i can't synchronize the internal clk to both camera's.

Altho both are working on 48MHz. And the FPGA will work at 100MHz. Cauze FPGA must handle both camera's at the same time.