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Altera_Forum
Honored Contributor
Honored ContributorAsynchronous data
hi agin, I whant to clock in data at the rate of 48MHz (Camera). At the falling edge of the PIX_CLK data is valid. My design will work at 48MHz but the both clk's wont be synchronised...
Altera_ForumHonored Contributor
Honored ContributorBut the two domains are at the same clkfreq. Wont this be a waist of
resources? Or is the use of a small fifo not that bad ?
