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Altera_Forum's avatar
Altera_Forum
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15 years ago

Asynchronous data

hi agin, I whant to clock in data at the rate of 48MHz (Camera). At the falling edge of the PIX_CLK data is valid. My design will work at 48MHz but the both clk's wont be synchronised...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

unless they are synchronised, you will have to assume each clock domain is completly seperate, and hence a fifo is required.