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Altera_Forum
Honored Contributor
Honored ContributorAsynchronous data
hi agin, I whant to clock in data at the rate of 48MHz (Camera). At the falling edge of the PIX_CLK data is valid. My design will work at 48MHz but the both clk's wont be synchronised...
Altera_ForumHonored Contributor
Honored ContributorIt is well known practice in multiple video inputs to use fifos. One fifo to bridge data from camera1 to the 100MHz and the second fifo to bridge the other camera.
IN the 100MHz domain you can then time mux the data if you wish serial processing as two channels. I don't foresee any problems.
