Advices on VHDL signals initialization (Quartus synthesis vs Modelsim simulation)

Question

Hi everybody,

I use Modelsim to simulate my VHDL design, and when declaring signals I usually don't add any initialization since I know that inside the FPGA the logic is "automatically" initialized after the device exits from POR.

Unfortunately this is becoming an issue with Modelsim since to "safely" run the simulation all the signals should be initialized, generally to '0' or (others => '0'). Up to now I've worked by adding initializations to all signals when using the file in Modelsim, and commenting them away when using them in my Quartus project:

signal a : std_logic; --Quartus

signal a : std_logic := '0'; --Modelsim

Now I'm wondering: from the Quartus synthesis point of view is it advisable to initialize ALL the signals when declaring them in my VHDL? Will Quartus treat all the signals initialized to '0' in the same way as the uninitialized ones?

This way I could avoid adding/working with the 2 versions of each files (with and without signals initialization).

Any suggestion?

Thank you very much for your help :)

Claudio

altera_forum · Answer

Quartus can use the initilised values no problem - it gives the registers their power up value. It will also initialise registers from their async reset value. Unitialised signals can be set to either '0' or '1' at power up.

I would never work with two versions of the same file.

altera_forum · Answer

Tools have their own mind and history. In the past, any initialisation in vhdl code was ignored. Now I hear it is seen as you want it so.

For initial values, additionally there is tool setting (power up don't care ON or OFF) lets you do that and may be this or vhdl overrides, not sure.

initial values in modelsim can be left as undefined until they get driven, this shouldn't harm except in some cases e.g. accumulator stays undefined as it lives with initial undefined value.

In any case of having different code when targetting synthesis and sim you can easily set translate switch in same file

altera_forum · Answer

Thank you all for the answers. At the moment I will keep all the initializations, then I will check if some unwanted overhead logic is added after Quartus compilation.

Kaz, what do you mean with "you can easily set translate switch in same file"? Could you please make an example? Thanks!

altera_forum · Answer

The translate_off and translate_on synthesis directives indicate whether the Quartus II software or a third-party synthesis tool should compile a portion of HDL code that is not relevant for synthesis. The translate_off directive marks the beginning of code that the synthesis tool should ignore; the translate_on directive indicates that synthesis should resume. You can also use the synthesis_on and

synthesis_off directives as a synonym for translate on and off

e.g. (try this, not tested)

signal x : integer translate_off := 10 translate_on;

altera_forum · Answer

translate_off/on doesnt quite work like that. They are plaed inside comments embedded within the code, like this:  
--synthesis translate_off
signal a : integer; -- synthesisor will not see signal a
--synthesis translate_on
  you cannot embed translate_on/off in the middle of a line, you'll get a syntax error.

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Advices on VHDL signals initialization (Quartus synthesis vs Modelsim simulation)

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