Advices on VHDL signals initialization (Quartus synthesis vs Modelsim simulation)

Quartus can use the initilised values no problem - it gives the registers their power up value. It will also initialise registers from their async reset value. Unitialised signals can be set to either '0' or '1' at power up.

Tools have their own mind and history. In the past, any initialisation in vhdl code was ignored. Now I hear it is seen as you want it so.

Thank you all for the answers. At the moment I will keep all the initializations, then I will check if some unwanted overhead logic is added after Quartus compilation.

The translate_off and translate_on synthesis directives indicate whether the Quartus II software or a third-party synthesis tool should compile a portion of HDL code that is not relevant for synthesis. The translate_off directive marks the beginning of code that the synthesis tool should ignore; the translate_on directive indicates that synthesis should resume. You can also use the synthesis_on and

translate_off/on doesnt quite work like that. They are plaed inside comments embedded within the code, like this:

--synthesis translate_off
signal a : integer; -- synthesisor will not see signal a
--synthesis translate_on

these translate_on/off are mostly used to hide debug code from the synthesisor (often stuff that will be no way synthesisable, like fileIO).

Tricky, being too lazt to test sorry, would it work like this:

should do (but dont forget the synthesis bit).

you might also find read comments as synthesis HDL useful