Advices on VHDL signals initialization (Quartus synthesis vs Modelsim simulation)

Tools have their own mind and history. In the past, any initialisation in vhdl code was ignored. Now I hear it is seen as you want it so.

For initial values, additionally there is tool setting (power up don't care ON or OFF) lets you do that and may be this or vhdl overrides, not sure.

initial values in modelsim can be left as undefined until they get driven, this shouldn't harm except in some cases e.g. accumulator stays undefined as it lives with initial undefined value.

In any case of having different code when targetting synthesis and sim you can easily set translate switch in same file