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Altera_Forum
Honored Contributor
Honored ContributorAdvices on VHDL signals initialization (Quartus synthesis vs Modelsim simulation)
Hi everybody, I use Modelsim to simulate my VHDL design, and when declaring signals I usually don't add any initialization since I know that inside the FPGA the logic is "automatically" initial...
Altera_ForumHonored Contributor
Honored ContributorThank you all for the answers. At the moment I will keep all the initializations, then I will check if some unwanted overhead logic is added after Quartus compilation.
Kaz, what do you mean with "you can easily set translate switch in same file"? Could you please make an example? Thanks!
