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Altera_Forum
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14 years ago

Advices on VHDL signals initialization (Quartus synthesis vs Modelsim simulation)

Hi everybody, I use Modelsim to simulate my VHDL design, and when declaring signals I usually don't add any initialization since I know that inside the FPGA the logic is "automatically" initial...
Altera_Forum's avatar
Altera_Forum
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14 years ago

translate_off/on doesnt quite work like that. They are plaed inside comments embedded within the code, like this: 


--synthesis translate_off
signal a : integer; -- synthesisor will not see signal a
--synthesis translate_on

you cannot embed translate_on/off in the middle of a line, you'll get a syntax error.