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Altera_Forum
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14 years ago

Advices on VHDL signals initialization (Quartus synthesis vs Modelsim simulation)

Hi everybody, I use Modelsim to simulate my VHDL design, and when declaring signals I usually don't add any initialization since I know that inside the FPGA the logic is "automatically" initial...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Quartus can use the initilised values no problem - it gives the registers their power up value. It will also initialise registers from their async reset value. Unitialised signals can be set to either '0' or '1' at power up.

I would never work with two versions of the same file.