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Honored Contributor
Honored ContributorAdvices on VHDL signals initialization (Quartus synthesis vs Modelsim simulation)
Hi everybody, I use Modelsim to simulate my VHDL design, and when declaring signals I usually don't add any initialization since I know that inside the FPGA the logic is "automatically" initial...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- At the moment I will keep all the initializations, then I will check if some unwanted overhead logic is added after Quartus compilation. --- Quote End --- It won't. All registers have a power-on default state of "zero", if you initialize a register signal to "one", an inverter will be placed after the register in the synthesized netlist ("not pushback"). A problem arises, if you want both asnychronous set and reset for a register signal. Quartus needs to implement an additional latch and XOR logic to emulate the asynchronous set/reset. A warning will indicate this.
