Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAdvices on VHDL signals initialization (Quartus synthesis vs Modelsim simulation)
Hi everybody, I use Modelsim to simulate my VHDL design, and when declaring signals I usually don't add any initialization since I know that inside the FPGA the logic is "automatically" initial...
Altera_ForumHonored Contributor
Honored Contributorthese translate_on/off are mostly used to hide debug code from the synthesisor (often stuff that will be no way synthesisable, like fileIO).
