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Altera_Forum
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14 years ago

Advices on VHDL signals initialization (Quartus synthesis vs Modelsim simulation)

Hi everybody, I use Modelsim to simulate my VHDL design, and when declaring signals I usually don't add any initialization since I know that inside the FPGA the logic is "automatically" initial...
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Altera_Forum
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14 years ago

The translate_off and translate_on synthesis directives indicate whether the Quartus II software or a third-party synthesis tool should compile a portion of HDL code that is not relevant for synthesis. The translate_off directive marks the beginning of code that the synthesis tool should ignore; the translate_on directive indicates that synthesis should resume. You can also use the synthesis_on and

synthesis_off directives as a synonym for translate on and off

e.g. (try this, not tested)

signal x : integer translate_off := 10 translate_on;