a strange problem!

module zhengxing(clk_200M,

rst,

data_in,

data_out

);

input clk_200M;

input rst;

input data_in;

output data_out;

reg data_out;

reg [2:0]counter;

reg [1:0]state;

parameter low=2'b00,

wait_high=2'b01,

high=2'b10,

wait_low=2'b11;

always @ (posedge clk_200M or posedge rst)

if(rst==1)

begin counter<=0;

data_out<=0;

state<=low;

end

else case(state)

low:if(counter>=3)

begin data_out<=0;

state<=wait_high;

end

else begin counter<=counter+1;

// data_out<=1;

state<=low;

end

wait_high:if(data_in==1)

begin state<=high;

counter<=0;

///data_out<=0;

end

else begin

state<=wait_high;

counter<=0;

//data_out<=0;

end

high:if(counter>=3)

begin data_out<=1;

state<=wait_low;

end

else begin state<=high;

counter<=counter+1;

end

wait_low:if(data_in==0)

begin state<=low;

counter<=0;

end

else begin state<=wait_low;

counter<=0;

end

default:state<=low;

endcase

endmodule

there is no error in it.and the simulation is also right ,but when it is in the fpga ,it doesn't work.and the out port is always high ; i don't know it's why! who can help me? thank you!