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Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Unexpected behaviour of DDR3 SDRAM ready and data_valid signals

Hi,

I am trying to configure DDR3 SDRAM controller with uniphy IP and NIOS II with my custom RTL code. This custom RTL codes generates read/write req with an interface data width of 128 bits.

I have attached all the settings I have selected in SDRAM IP, in snapshots(Capture 1,2,3,4).

Problem I am facing: When I generate read req for a burst size of any(say 10), I was exptecting SDRAM to give me data(total of 128 x 10 = 1280 bits) in 10 clock cycles . But I am getting data in different chunks( 128 bits in every 3 or 4 clock cycles), instead of single burst(128 bits in every clock cycles 10 times). This has degraded the performance of my design drastically.

I have also attached the stp result screenshot(result.png) which explains the problem .

Please let me know what is the mistake I might be doing , and how to resolve this so I get 128 bits data every clock cycle.

regards,

Yogesh

14 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Unless I'm looking at your parameter settings incorrectly, your external memory interface width is set to 32 bits. As such, it would take 4 cycles to get a full 128 bits for a read transfer. The Platform Designer interconnect buffers up the read data to provide the full 128 bits to the host (presumably a Nios processor). The 128 bits is for the internal Avalon interface, not the external memory interface.

    • Yogesh's avatar
      Yogesh
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago
      Hi,
      Could you please tell me what should be the correct parameter settings to resolve this issue?

      regards,
      Yogesh
    • Yogesh's avatar
      Yogesh
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      @sstrell one more thing I want to add here, Whatever you said makes sense but frequency is also playing role here.

      The external memory interface width is 32 bits, but it is DDR running at 300 MHZ.

      So at 300MHZ we are getting 64 bits and as AFI clock is 150 MHZ, we should get 128 bits per clock cycle.

      Now my design is running at 50 MHZ with a interconnect IP in between, connecting SDRAM and MY IP.

      In that case also I should get continuous data and VALID/READY signal.

      This is my understanding, please correct me if I am wrong.

      • yoichiK_altera's avatar
        yoichiK_altera
        Icon for Contributor rankContributor
        5 years ago

        AFI clock is 150Mhz and user design is running 50Mhz, I presume there is avalon MM clock crossing bridge as interconnect between AFI and user clock. Can you check how many burst counts is set in the interconnect ? If that is set only one you should change to 4 or more.

    • Yogesh's avatar
      Yogesh
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      @yoichiK_intel No I havn't done any simulation with SDRAM IP yet, but on board I am getting correct data.

      Can you please guide me how I can run simulation of my IP with SDRAM IP in QSYS as I am new to INTEL tools?