Forum Discussion
Occasional ContributorUnexpected behaviour of DDR3 SDRAM ready and data_valid signals
Super ContributorUnless I'm looking at your parameter settings incorrectly, your external memory interface width is set to 32 bits. As such, it would take 4 cycles to get a full 128 bits for a read transfer. The Platform Designer interconnect buffers up the read data to provide the full 128 bits to the host (presumably a Nios processor). The 128 bits is for the internal Avalon interface, not the external memory interface.
Occasional Contributor@sstrell one more thing I want to add here, Whatever you said makes sense but frequency is also playing role here.
The external memory interface width is 32 bits, but it is DDR running at 300 MHZ.
So at 300MHZ we are getting 64 bits and as AFI clock is 150 MHZ, we should get 128 bits per clock cycle.
Now my design is running at 50 MHZ with a interconnect IP in between, connecting SDRAM and MY IP.
In that case also I should get continuous data and VALID/READY signal.
This is my understanding, please correct me if I am wrong.
