Occasional Contributor
Super ContributorUnless I'm looking at your parameter settings incorrectly, your external memory interface width is set to 32 bits. As such, it would take 4 cycles to get a full 128 bits for a read transfer. The Platform Designer interconnect buffers up the read data to provide the full 128 bits to the host (presumably a Nios processor). The 128 bits is for the internal Avalon interface, not the external memory interface.
Occasional Contributor@sstrell one more thing I want to add here, Whatever you said makes sense but frequency is also playing role here.
The external memory interface width is 32 bits, but it is DDR running at 300 MHZ.
So at 300MHZ we are getting 64 bits and as AFI clock is 150 MHZ, we should get 128 bits per clock cycle.
Now my design is running at 50 MHZ with a interconnect IP in between, connecting SDRAM and MY IP.
In that case also I should get continuous data and VALID/READY signal.
This is my understanding, please correct me if I am wrong.
ContributorAFI clock is 150Mhz and user design is running 50Mhz, I presume there is avalon MM clock crossing bridge as interconnect between AFI and user clock. Can you check how many burst counts is set in the interconnect ? If that is set only one you should change to 4 or more.
Occasional ContributorYes there is a Interconnect IP, which QSYS puts by default but there is no option to control burst length in that.
But there is a option of "Maximum Burst Length" in SDRAM IP, which is by default set to 4 in SDRAM IP -> controller settings. (Please find attached screenshot of the same)
As per the External Memory Interface Handbook Volume 2:
Page - 328 says that this "Maximum Burst Length" parameter affects the FIFO parameters in Interconnect.
We tried changing it from 4 to 128, still can't see any improvement.
Can you suggest what may be going wrong, which can explain why each transaction in a burst is taking 3 clock cycles, so a burst length of 256 is eventually taking 256*3 = 768 clock cycles.
ContributorCan you replace the interconnect IP to Avalong-MM Clock Crossing Bridge IP from current one ? By default qsys insert interconnect IP without FiFo and burst read/write will be chopped in the interconnect IP.
