yoichiK_altera
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Re: EMIF Pin Assignment for Agilex 7 FPGA I-Series DevKit (DK-DEV-AGI027R1BES)
Coping from devkit user guide. The slot support only 2-DPC(dual per channel) thus J1 and J2 signals are shared across dual dimms beside CS/ODT/CKE. The two 288-pin DIMM sockets interface to bank 3C, 3D for Dual DIMM memory. These sockets accept DDR4 module. These DIMM support dual rank at frequency 1333 MHZ 16 GB per channel, and single rank at 1333 MHZ 8 GB per channel. — Some board re-work is required for using DIMM sockets in 2-DPC configuration or different kinds of DDR4 modules. For more details of the resistor connections required to be present for the type of configuration used, refer to board schematic table. Do you want to enable 2-DPC configuration ? or just 1-DPC which can be generated from example design.25Views0likes6CommentsRe: Agilex 5 EMIF-LPDDR4, AXI4 Read-Write Starvation Issue
I tried to replicate the issue at my side with Agilex5E devkit. and did similar data traffic on hardware. I use async mode at AXI interface and burst length is 2 with consecutive write access. During consecutive write access one read access is issued and I see rvalid is returned before completion of consecutive write access.33Views0likes0CommentsRe: Agilex 5 EMIF-LPDDR4, AXI4 Read-Write Starvation Issue
Agilex5 EMIF IP controller tries to maximize the efficiency based on coming traffic data pattern and user can not control starvation and reordering option. Thus in that your case completing the sequential write command then read command is processed. You may want to order write and read command separately at AXi bus interface ie issue read command after write command .50Views0likes2Comments