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yoichiK_altera
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Re: SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design
The 390.625 MHz SyncE-recovered clock is used on the evaluation kit primarily because it is a high-quality, system-level frequency reference that is already available from the Ethernet/CPRI clocking subsystem—not because DDR5 or HBM inherently require a SyncE source.13Views0likes0CommentsRe: Memory Support with A5ED065BB32AI4S Agilex5 FPGA
Hi Jay Please see my comments here For PL X32+ECC with the 2A,X32+ECC with the 2B bank. --> yes. For PS X32+ECC with the 3A,X32+ECC with the 3B bank . -->No, If only one IO96 bank is to be used by HPS-EMIF, it must be the one adjacent to the HPS MPFE. (Bank 3A.)35Views0likes2CommentsRe: Memory Support with A5ED065BB32AI4S Agilex5 FPGA
Jay For the A5ED065BB32AI4S (Agilex 5 E-Series SoC), the HPS EMIF cannot be placed in arbitrary banks such as 2A/2B/3A/3B. The HPS DDR interface uses dedicated EMIF resources hard-wired to specific HSIO banks located adjacent to the HPS block. Please check the following link for HPS subsystem and bridge system interation. https://docs.altera.com/r/docs/817467/26.1/external-memory-interfaces-emif-ip-user-guide-agilextm-5-fpgas-and-socs/agilextm-5-emif-ip-for-hard-processor-subsystem-hps https://docs.altera.com/r/docs/814346/26.1/hard-processor-system-technical-reference-manual-agilextm-5-socs/bridges-system-integration54Views0likes4CommentsRe: Error(13135): Address/command pin is constrained to an illegal location
Hello Masaru There is DDR3 example design targeting Cyclone10GX devkit(version B) and see no fitter error with placing ddr3_a[0] at PIN_AG19. Please download the DDR3 design from below link. c10gx-10cx220yf780-revb-v22.4b94-v1.0\examples\ddr3x40 https://docs.altera.com/v/u/resources/838158/cyclone-10-gx-fpga-development-kit-version-b-dk-dev-10cx220-b-installer-package-v22.4-or-higher37Views0likes1Comment