yoichiK_altera
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Re: Agilex 5 EMIF-LPDDR4, AXI4 Read-Write Starvation Issue
I tried to replicate the issue at my side with Agilex5E devkit. and did similar data traffic on hardware. I use async mode at AXI interface and burst length is 2 with consecutive write access. During consecutive write access one read access is issued and I see rvalid is returned before completion of consecutive write access.24Views0likes0CommentsRe: Agilex 5 EMIF-LPDDR4, AXI4 Read-Write Starvation Issue
Agilex5 EMIF IP controller tries to maximize the efficiency based on coming traffic data pattern and user can not control starvation and reordering option. Thus in that your case completing the sequential write command then read command is processed. You may want to order write and read command separately at AXi bus interface ie issue read command after write command .37Views0likes2CommentsRe: Why 10AS016C4U19E3SG could use the x16 DDR4 component upper byte lane[DQ8~DQ15] for ECC?
Hi The restrictions on I/O bank usage result from the Arria® 10 HPS having hard-wired connections to the EMIF circuits in the I/O banks closest to the HPS. For any given EMIF configuration, the pin-out of the EMIF-to-HPS interface is fixed. Please refer to the following link for the detail. https://www.intel.com/content/www/us/en/docs/programmable/683106/24-1-19-2-3/restrictions-on-i-o-bank-usage-for-emif-19588.html369Views0likes0CommentsRe: How to manually trigger or inhibit periodic OCT updates in Arria 10
I was bit inaccurate. not oct_cal_req ,but r_oct_cal_req signal in the RTL to disable it. oct_cal_req is the signal used during the power up. Here is the example RTL change to disable periodic OCT update. always_ff @(posedge w_oct_clock) begin if (w_oct_reset == 1'b1) begin r_oct_recal_timer[(OCT_RECAL_TIMER_WIDTH-1)] <= 1'b0; r_oct_recal_timer[(OCT_RECAL_TIMER_WIDTH-2):0] <= OCT_RECAL_TIMER_PRESET[(OCT_RECAL_TIMER_WIDTH-2):0]; r_oct_recal_req <= 1'b0; end else if (user_oct_disalbe) // added, user interface signal. r_oct_recal_req <= 1'b0; // added, disable periodic OCT else begin if (r_oct_recal_timer[(OCT_RECAL_TIMER_WIDTH-1)] == 1'b1) begin r_oct_recal_timer[(OCT_RECAL_TIMER_WIDTH-1)] <= 1'b0; r_oct_recal_timer[(OCT_RECAL_TIMER_WIDTH-2):0] <= OCT_RECAL_TIMER_PRESET[(OCT_RECAL_TIMER_WIDTH-2):0]; r_oct_recal_req <= ~r_oct_recal_req; end else begin r_oct_recal_timer[(OCT_RECAL_TIMER_WIDTH-1):0] <= r_oct_recal_timer[(OCT_RECAL_TIMER_WIDTH-1):0] - {{(OCT_RECAL_TIMER_WIDTH-1){1'b0}}, 1'b1}; end end end1.3KViews1like0CommentsRe: calibration of ddr4 interface on 10AX066H4F34E3SG
Hi You can download the PCB layout of arria 10 soc development kit from the link here https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/arria10/soc/Production_files/arria10_10as066n3f40_soc_v15.1.2.zip1.4KViews0likes0CommentsRe: Quartus Pro 21.1 emif IP generation for Agilex device fails
This may not be related ,but did you check this KDB ? https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/emif/2021/error--no-such-variable--read-trace-on----env-iprootdir----invok.html785Views0likes0Comments