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Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Unexpected behaviour of DDR3 SDRAM ready and data_valid signals

Hi, I am trying to configure DDR3 SDRAM controller with uniphy IP and NIOS II with my custom RTL code. This custom RTL codes generates read/write req with an interface data width of 128 bits. I ha...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

Unless I'm looking at your parameter settings incorrectly, your external memory interface width is set to 32 bits. As such, it would take 4 cycles to get a full 128 bits for a read transfer. The Platform Designer interconnect buffers up the read data to provide the full 128 bits to the host (presumably a Nios processor). The 128 bits is for the internal Avalon interface, not the external memory interface.