Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

Hello,
I am developing a custom PCIe endpoint using the Agilex 7 R-Tile PIPE Direct interface. The PHY is provided by the R-Tile IP, while the LTSSM, Data Link Layer, and TLP/DLLP handling are implemented in soft RTL.

Environment

• FPGA: Agilex 7 AGIB027R29A
• Quartus Prime Pro 24.3.0 Build 212
• R-Tile PIPE Direct mode
• PCIe Gen3 x8
• Custom soft LTSSM and Data Link Layer
• Linux host with a commercial PC/root complex
• The FPGA is configured before a host cold boot
• The endpoint is not currently visible in lspci

In a successful Signal Tap capture:

1. The LTSSM reaches Gen3 L0.
2. The Data Link Layer reaches DL_ACTIVE.
3. InitFC1 and InitFC2 for Posted, Non-Posted, and Completion traffic are exchanged.
4. We observe valid incoming TLP traffic with a correct LCRC.
5. The host sends a Message TLP that appears to decode as Set_Slot_Power_Limit.
6. No subsequent Configuration Type 0 Read TLP or other expected enumeration TLP is observed.
7. The link later returns from L0 to Recovery.RcvrLock.

Our understanding is that Set_Slot_Power_Limit is a posted Message TLP and should not require a Completion TLP from the endpoint. The endpoint should only acknowledge successful reception at the Data Link Layer. Please correct us if this interpretation is wrong.

Questions

1. Is receiving Set_Slot_Power_Limit before the first Configuration Read a normal root-port enumeration sequence?
2. Does the endpoint need to respond to this Message TLP in any way other than sending a Data Link Layer ACK?
3. If the ACK DLLP has an incorrect sequence number, CRC, or timing, could the root port stop sending further TLPs and eventually force the link into Recovery?
4. Are there any R-Tile PIPE Direct-specific status or control signals that must be handled before the host starts Configuration transactions?
5. Are there recommended R-Tile debug signals for determining why the root port stops after this message?
6. Could an incorrect Flow Control advertisement—especially Completion Header/Data credits—cause this behavior even if InitFC2 completes?
7. Are there known PERST#, cold-boot, or FPGA-configuration timing requirements for enumeration when using PIPE Direct mode?

We are currently capturing the following signals:

• LTSSM state
• Data Link Layer state
• InitFC1/InitFC2 and UpdateFC status
• Received TLP Fmt/Type and complete header
• Received TLP sequence number
• LCRC result
• ACK/NAK request and transmitted ACK/NAK sequence number
• Replay timer/replay status
• RX block lock, CDR lock, and lane numbers
• Raw 1024-bit PIPE RX block data

Any guidance on the expected transaction sequence after Set_Slot_Power_Limit, or additional signals that should be captured, would be greatly appreciated.

Thank you.