Unexpected behaviour of DDR3 SDRAM ready and data_valid signals

Unless I'm looking at your parameter settings incorrectly, your external memory interface width is set to 32 bits. As such, it would take 4 cycles to get a full 128 bits for a read transfer. The Platform Designer interconnect buffers up the read data to provide the full 128 bits to the host (presumably a Nios processor). The 128 bits is for the internal Avalon interface, not the external memory interface.