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Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Unexpected behaviour of DDR3 SDRAM ready and data_valid signals

Hi, I am trying to configure DDR3 SDRAM controller with uniphy IP and NIOS II with my custom RTL code. This custom RTL codes generates read/write req with an interface data width of 128 bits. I ha...
yoichiK_altera's avatar
yoichiK_altera
Icon for Contributor rankContributor
5 years ago

Did you run the simulation and see same behavior ?

  • Yogesh's avatar
    Yogesh
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    @yoichiK_intel No I havn't done any simulation with SDRAM IP yet, but on board I am getting correct data.

    Can you please guide me how I can run simulation of my IP with SDRAM IP in QSYS as I am new to INTEL tools?