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Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Timing violation when use Triple speed Ethernet IP

Hi,

In my design, I use Cyclone V SoC and I need 4 ethernet channels, so I have to use Triple Speed Ethernet IP the extra channels HPS can not provide.

I referred to the example design (Niosii_ethernet_standard_3c120_rgmii.zip) and the timing constraint guide an433 and an477.

It looks like the timing constraint setting by the example is different from the description described in the guide an477, I tried both the way of an477 and the timing used in the example (I set optimization to “speed” already), neither of them pass the timing.

In the example design and my design, it only uses delay in external PHY, this means tx is edge-aligned and same edge, and rx is center-aligned and same edge in fpga.

The differences in the example design and an477 is: in the example design, no multicycle constraint is set, but in an477 and an433, the multicycle constraint should be set for tx path.

I analyzed the failed path, it looks like the data path right before clkctrl_G3 (clockbuffer) is extremely long. (See the picture attached)

Well, I do not understand why this is so long and do not know how to solve it. I’m thinking about set location constraint for this buffer, then I found out this is the closest buffer already.

The tx_clk is assigned by the following sentences:

tx_clk <= enet_tx_125 when eth_mode = '1' else -- 1G

enet_tx_2p5 when ena_10 = '1' else -- 10 Mb

enet_tx_25; -- 100Mb Mode = 25MHz clock

Therein enet_tx_125, enet_tx_2p5 and enet_tx_25 are pll outputs.

I also tried tx_clk <= enet_tx_125 to get rid of the combinational control of clock, but I did not get any progress.

Then I tried center-aligned strategy for tx-path by using PLL to phase shift tx clock output, the timing is even worse.

I'm stuck here, I need help now. My project is compiled in Quartus 18.1, and the qar file is attached here.

Any reply or response is appreciate.

Best wishes

Jasmine

8 Replies

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    Hi Sir, I would suggest you to refer the AN647 for Cyclone V design to constrain the RGMII, you can get the design from the link below: https://www.intel.com/content/www/us/en/programmable/support/support-resources/intellectual-property/interface-protocols/triple-speed-ethernet/ips-inp-tse.html Here is the recommendation to your design: 1. Remove the derive_pll_clocks since all the PLL output clock are manual created 2. Use this to create clock for tx_clk_*: create_generated_clock -name tx_clk_125 \ -source [get_pins {pll_0|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] \ [get_pins {soc_inst|pll_0|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] create_generated_clock -name tx_clk_25 \ -source [get_pins {pll_0|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] \ [get_pins {soc_inst|pll_0|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -divide_by 5 create_generated_clock -name tx_clk_2_5 \ -source [get_pins {pll_0|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] \ [get_pins {soc_inst|pll_0|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -divide_by 50 3. Use this to create clock for enet_gtx_clk_* create_generated_clock -name enet_gtx_clk_125 -source [get_pins {tx_clk|combout}] -master_clock {tx_clk_125} -add [get_ports {fpga_enet2_gtx_clk}] create_generated_clock -name enet_gtx_clk_25 -source [get_pins {tx_clk|combout}] -master_clock {tx_clk_25} -add [get_ports {fpga_enet2_gtx_clk}] create_generated_clock -name enet_gtx_clk_2_5 -source [get_pins {tx_clk|combout}] -master_clock {tx_clk_2_5} -add [get_ports {fpga_enet2_gtx_clk}] Regards -SK Lim
    • Mingyuexin's avatar
      Mingyuexin
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi,

      Thank you very much for the quick response. I will try your suggestions and see.

      Best wishes

      Jasmine

    • Mingyuexin's avatar
      Mingyuexin
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi again,

      I change the constraint for tx_clk*and enet_gtx_clk_* according to your suggestions, though I need to adjust it slightly to make it apply my case because the input clock for my pll is 50 MHz instead of 125 Hz.

      I had a look at AN647 and the example design for Cyclone V GX.

      It looks like the constraint set in the design is center-aligned for tx channel, but the tx clock does not have phase shift at all. In the design, it's actually edge-aligned for tx channel. So I'm very confused here.

      Other than that, the setting for rx channels is different from AN477 also.

      Until now, the example I mentioned (Niosii_ethernet_standard_3c120_rgmii.zip), the example described in AN647 and AN477 (and AN433) have conflictions, and I'm very confused now.

      What can I do to improve the timing violation? What is the next step I can try?

      Best wishes

      Jasmine

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    ​Hi Jasmine, Yes, the RGMII timing constraint is not straight forward, and it depends whether you have enable the central align from the external PHY. You can follow AN647 or other newer design from Design store to do the constraint, and then the most importantly is it can pass the hardware testing.

    Regards -SK

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    ​For the TX, you can refer to my previous suggestion. For RX, you can try to add following setting in the .qsf file.

    set_instance_assignment -name GLOBAL_SIGNAL OFF -to fpga_enet2_rx_clk

  • Mingyuexin's avatar
    Mingyuexin
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi,

    My timing violation is caused by the TX path.

    I read AN647 and have a close look at the example design for Cyclone V.

    I noticed in the example design, TX is edge-aligned, i.e. there is no TX clock delay in FPGA.

    However, the timing constraint is not set according to AN433 and AN477.

    In AN477, the Tsu and Th is -0.9 and 2.7 respectively when enabling delay for PHY (Marvel 88EE1111) . Also multicycle path should be set for TX path, see page 14 of AN477. If multi cycle path is not set, then extra delay should be added when set output delay (See page 14 of AN433 ). Apparently, AN647 example neither set multi cycle path, nor adds extra delay. In stead, it sets output delay according to Page 10 of AN477, which is for center aligned TX path, but the center aligned TX path needs TX clock has phase shift of 90, which AN647 example does not have.

    Since AN647 example does not set multi cycle path, so it passes timing constraint. If I set multi cycle for TX path according to AN477, the timing fails too.

    I removed multi cycle path setting for TX path in my design, change Tsu and Th to 1.0 and -0.8. The timing violation is gone. I can understand why the timing is closed after multi cycle setting is removed.

    Now my question is:

    Was AN647 example tested and worked successfully, does it mean AN477 and AN433 are actually wrong guide?

    Thank you very much in advance!

    Best regards

    Jasmine

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    ​The example design in AN647 and the cyclone 10 LP designs are tested in hardware and worked successfully.

    Regards -SK