Timing violation when use Triple speed Ethernet IP

Hi Sir, I would suggest you to refer the AN647 for Cyclone V design to constrain the RGMII, you can get the design from the link below: https://www.intel.com/content/www/us/en/programmable/support/support-resources/intellectual-property/interface-protocols/triple-speed-ethernet/ips-inp-tse.html Here is the recommendation to your design: 1. Remove the derive_pll_clocks since all the PLL output clock are manual created 2. Use this to create clock for tx_clk_*: create_generated_clock -name tx_clk_125 \ -source [get_pins {pll_0|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] \ [get_pins {soc_inst|pll_0|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] create_generated_clock -name tx_clk_25 \ -source [get_pins {pll_0|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] \ [get_pins {soc_inst|pll_0|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -divide_by 5 create_generated_clock -name tx_clk_2_5 \ -source [get_pins {pll_0|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] \ [get_pins {soc_inst|pll_0|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -divide_by 50 3. Use this to create clock for enet_gtx_clk_* create_generated_clock -name enet_gtx_clk_125 -source [get_pins {tx_clk|combout}] -master_clock {tx_clk_125} -add [get_ports {fpga_enet2_gtx_clk}] create_generated_clock -name enet_gtx_clk_25 -source [get_pins {tx_clk|combout}] -master_clock {tx_clk_25} -add [get_ports {fpga_enet2_gtx_clk}] create_generated_clock -name enet_gtx_clk_2_5 -source [get_pins {tx_clk|combout}] -master_clock {tx_clk_2_5} -add [get_ports {fpga_enet2_gtx_clk}] Regards -SK Lim