Forum Discussion
Mingyuexin
Occasional Contributor
Occasional ContributorTiming violation when use Triple speed Ethernet IP
Hi, In my design, I use Cyclone V SoC and I need 4 ethernet channels, so I have to use Triple Speed Ethernet IP the extra channels HPS can not provide. I referred to the example design (Niosii_e...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi Jasmine, Yes, the RGMII timing constraint is not straight forward, and it depends whether you have enable the central align from the external PHY. You can follow AN647 or other newer design from Design store to do the constraint, and then the most importantly is it can pass the hardware testing.
Regards -SK
MingyuexinHi SK,
As I said, AN647's design (edge_aligned) and timing constraint (center_aligned) are not consistent.
I took the following link as reference. There is still big timing violation in my design. My project is attached.
https://fpgacloud.intel.com/devstore/platform/?search=triple&acds_version=any&family=cyclone-10-lp
What else I can try?
