Timing violation when use Triple speed Ethernet IP

Hi,

My timing violation is caused by the TX path.

I read AN647 and have a close look at the example design for Cyclone V.

I noticed in the example design, TX is edge-aligned, i.e. there is no TX clock delay in FPGA.

However, the timing constraint is not set according to AN433 and AN477.

In AN477, the Tsu and Th is -0.9 and 2.7 respectively when enabling delay for PHY (Marvel 88EE1111) . Also multicycle path should be set for TX path, see page 14 of AN477. If multi cycle path is not set, then extra delay should be added when set output delay (See page 14 of AN433 ). Apparently, AN647 example neither set multi cycle path, nor adds extra delay. In stead, it sets output delay according to Page 10 of AN477, which is for center aligned TX path, but the center aligned TX path needs TX clock has phase shift of 90, which AN647 example does not have.

Since AN647 example does not set multi cycle path, so it passes timing constraint. If I set multi cycle for TX path according to AN477, the timing fails too.

I removed multi cycle path setting for TX path in my design, change Tsu and Th to 1.0 and -0.8. The timing violation is gone. I can understand why the timing is closed after multi cycle setting is removed.

Now my question is:

Was AN647 example tested and worked successfully, does it mean AN477 and AN433 are actually wrong guide?

Thank you very much in advance!

Best regards

Jasmine