Forum Discussion

Occasional Contributor

7 years ago

Timing violation when use Triple speed Ethernet IP

Hi, In my design, I use Cyclone V SoC and I need 4 ethernet channels, so I have to use Triple Speed Ethernet IP the extra channels HPS can not provide. I referred to the example design (Niosii_e...

my_soc_design_one_tse_5csxfc6.qar4.4 MB

SengKok_L_Intel

Regular Contributor

7 years ago

For the TX, you can refer to my previous suggestion. For RX, you can try to add following setting in the .qsf file.

set_instance_assignment -name GLOBAL_SIGNAL OFF -to fpga_enet2_rx_clk

Forum Discussion

Timing violation when use Triple speed Ethernet IP

Recent Discussions

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

PCIe Root Complex on DK-A5E013BM16AEA

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work