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Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Timing violation when use Triple speed Ethernet IP

Hi, In my design, I use Cyclone V SoC and I need 4 ethernet channels, so I have to use Triple Speed Ethernet IP the extra channels HPS can not provide. I referred to the example design (Niosii_e...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

​For the TX, you can refer to my previous suggestion. For RX, you can try to add following setting in the .qsf file.

set_instance_assignment -name GLOBAL_SIGNAL OFF -to fpga_enet2_rx_clk