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Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Timing violation when use Triple speed Ethernet IP

Hi, In my design, I use Cyclone V SoC and I need 4 ethernet channels, so I have to use Triple Speed Ethernet IP the extra channels HPS can not provide. I referred to the example design (Niosii_e...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi Sir, I would suggest you to refer the AN647 for Cyclone V design to constrain the RGMII, you can get the design from the link below: https://www.intel.com/content/www/us/en/programmable/support/support-resources/intellectual-property/interface-protocols/triple-speed-ethernet/ips-inp-tse.html Here is the recommendation to your design: 1. Remove the derive_pll_clocks since all the PLL output clock are manual created 2. Use this to create clock for tx_clk_*: create_generated_clock -name tx_clk_125 \ -source [get_pins {pll_0|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] \ [get_pins {soc_inst|pll_0|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] create_generated_clock -name tx_clk_25 \ -source [get_pins {pll_0|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] \ [get_pins {soc_inst|pll_0|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -divide_by 5 create_generated_clock -name tx_clk_2_5 \ -source [get_pins {pll_0|pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] \ [get_pins {soc_inst|pll_0|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -divide_by 50 3. Use this to create clock for enet_gtx_clk_* create_generated_clock -name enet_gtx_clk_125 -source [get_pins {tx_clk|combout}] -master_clock {tx_clk_125} -add [get_ports {fpga_enet2_gtx_clk}] create_generated_clock -name enet_gtx_clk_25 -source [get_pins {tx_clk|combout}] -master_clock {tx_clk_25} -add [get_ports {fpga_enet2_gtx_clk}] create_generated_clock -name enet_gtx_clk_2_5 -source [get_pins {tx_clk|combout}] -master_clock {tx_clk_2_5} -add [get_ports {fpga_enet2_gtx_clk}] Regards -SK Lim
Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi again,

I change the constraint for tx_clk*and enet_gtx_clk_* according to your suggestions, though I need to adjust it slightly to make it apply my case because the input clock for my pll is 50 MHz instead of 125 Hz.

I had a look at AN647 and the example design for Cyclone V GX.

It looks like the constraint set in the design is center-aligned for tx channel, but the tx clock does not have phase shift at all. In the design, it's actually edge-aligned for tx channel. So I'm very confused here.

Other than that, the setting for rx channels is different from AN477 also.

Until now, the example I mentioned (Niosii_ethernet_standard_3c120_rgmii.zip), the example described in AN647 and AN477 (and AN433) have conflictions, and I'm very confused now.

What can I do to improve the timing violation? What is the next step I can try?

Best wishes

Jasmine