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Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Timing violation when use Triple speed Ethernet IP

Hi, In my design, I use Cyclone V SoC and I need 4 ethernet channels, so I have to use Triple Speed Ethernet IP the extra channels HPS can not provide. I referred to the example design (Niosii_e...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

​Hi Jasmine, Yes, the RGMII timing constraint is not straight forward, and it depends whether you have enable the central align from the external PHY. You can follow AN647 or other newer design from Design store to do the constraint, and then the most importantly is it can pass the hardware testing.

Regards -SK