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Elad0708's avatar
Elad0708
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1 year ago

DPX4 and DPx8 PHY

Hello,

I am trying to build a PHY for DisplayPort 5.4GHz design we have. I am trying to set Dp-PHY with 4-lanes and 8-lanes, I encountered couple of issues during the process:

  1. first how can I configure PHY from the IP catalog? I don't see that the dp protocol is in the PHY selection, while using direct PHY configuration.
  2. If I select the DisplayPort IP (PHY+Bitec decoder), I see that it only supports DP 4lanes. Can I configure the DP PHY to be 8 lanes?

I will appreciate your help on this subject.

Best Regards,

Elad Rotem

Fpga Devkit

18 Replies

  • zhenruan's avatar
    zhenruan
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    1 year ago

    Hi Elad,

    Please instance the DisplayPort Intel FPGA IP directly. You can generate the DisplayPort Example design after the IP generation. The Transceiver Native PHY Intel FPGA IP is included.

    The DisplayPort Intel FPGA IP can be set to 1,2,4 lane per the DisplayPort protocol. If the design needs 8 lanes please instance the DisplayPort Intel FPGA IP twice.

    Regards,

    Aaron

    • Elad0708's avatar
      Elad0708
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      1 year ago

      Appreciate your help on this!

      So, I follow your instructions and the project finish synthesis. Two question I have:

      1. Since I want to create 8-lanes and not two channels of DisplayPort, I created two instances of PHY. Both PHY's drive 'gxb_tx_clkout' so which one I should use? The DisplayPort controller should work only with one recovered clock.

      2. Also, the analog parameters (vod & emp) disturbed me, since DisplayPort controller will need to check this two PHYs separately.

      Can't I configure this one instance of PHY ('tx_phy_top' in the example design) to work with 8 lanes?

      Best Regards,

      Elad Rotem

      • zhenruan's avatar
        zhenruan
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        1 year ago

        Hi Elad,

        You can't instance one 8-channel Transceiver Native PHY to work with 2 HDMI interface (HDMI source/HDMI sink). The HDMI source/sink doesn't support the lane number exceeding 4.

        As the design needs 8 lanes DisplayPort, you can divide it into two groups. Each group works separately.

        One 4-lane DP sink IP needs one 4-channel Transceiver Native PHY RX IP.

        One 4-lane DP source IP needs one 4-channel Transceiver Native PHY TX IP.

        Regards,

        Aaron

  • Elad0708's avatar
    Elad0708
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    1 year ago

    Hi Aaron,

    I need to correct my initial question. I require an 8-lane DP Tx; there's no need for RX lanes since these differential lines are directly connected to the LCD panel.

    Essentially, my question pertains more to the 'gxb_tx_clkout' (link layer clock). We only need one clock for the control layer, not two from each PHY instantiation.

    Regards,

    Elad

    • zhenruan's avatar
      zhenruan
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      1 year ago

      Hi Elad,

      The design requires 8-lane DP Tx; You must set them into 2 interfaces. Each works at the tx-only mode and has a 4-lane DP source and a 4-channel Transceiver Native PHY TX IP. It also needs a AUX channel for the link training. That is defined in the DisplayPort protocol. The Intel DisplayPort IP just conforms the DisplayPort Standard. Please refer to the DisplayPort spec for more information.

      That also means there are two gxb_tx_clkout clocks in the design. You can't use one gxb_tx_clkout clock for the 8 channel PHY. Four channels form an HDMI interface that works together independently of the other four channels.

      Regards,

      Aaron

  • Elad0708's avatar
    Elad0708
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    1 year ago

    Hi Aaron,

    It is a little bit confusing; the question isn't only about DP. The question is about FPGA serdes regardless of DP. It is not DisplayPort by priority like the old spec iDP.

    Can we get this serdes configuration:

    • Non-DP,

    • 8 lanes single reference clock for all,

    • rate 5.4G similar to DP,

    • VSPE per lane similar to DP,

    • Max skew between all lanes 1000 pS

    The important thing for us is a single clock for all 8 lanes.

    Regards,

    Elad Rotem

    • zhenruan's avatar
      zhenruan
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      1 year ago

      Hi Elad,

      You can copy the 4-channel Transceiver Native PHY TX IP that generated for the DisplayPort example design (the rate is set to 5.4G) and modify the channel number from 4 to 8.

      Regards,

      Aaron

  • Elad0708's avatar
    Elad0708
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    1 year ago

    Hi Aaron,

    This was my first guess, but when I open the files tab in the example design generated, I see a file called 'dp_gxb_tx.qip' but there isn't any '*.ip' file.

    Is this the Transceiver Native PHY TX IP you mentioned?

    Elad

  • Elad0708's avatar
    Elad0708
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    1 year ago

    Hey,

    This is the IP listed under the generated example design folder :

    dp_0_example_design/rtl/core/ip/dp_tx/dp_tx_reset_bridge.ip
    dp_0_example_design/rtl/core/ip/dp_tx/dp_tx_mgmt_clk.ip
    dp_0_example_design/rtl/core/ip/dp_tx/dp_tx_clk_16.ip
    dp_0_example_design/rtl/core/ip/dp_tx/dp_tx_dp_source.ip
    dp_0_example_design/rtl/core/ip/dp_tx/dp_tx_mgmt_bridge.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_cpu_reset_bridge.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_dp_tx_reset_bridge.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_mgmt_clk.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_dp_tx_clk_16.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_cpu.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_onchip_mem.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_jtag_uart.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_sys_clock_timer.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_sysid.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_i2c_master.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_vvp_clock_bridge.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_vvp_reset_bridge.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_vvp_tpg.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_intel_vvp_cvo_0.ip
    dp_0_example_design/rtl/core/ip/dp_core/dp_core_intel_vvp_fr2cv_0.ip
    dp_0_example_design/rtl/tx_phy/dp_tx_data_fifo.ip
    dp_0_example_design/rtl/dp_gxb_syspll.ip
    dp_0_example_design/rtl/dp_iopll.ip
    dp_0_example_design/rtl/dp_pxl_iopll.ip
    dp_0_example_design/rtl/reset_release.ip

    I don't see any ip related to gxb_phy.. What am I missing?

    Thanks,

    Elad Rotem

  • HelenMa's avatar
    HelenMa
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    1 year ago

    Hi Elad,

    Which device are you using?

    Regards,

    Helen

  • Elad0708's avatar
    Elad0708
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    1 year ago

    Hi Helen,

    I am using DevKit- DKSIAGI027FC.

    Thanks,

    Elad Rotem

  • HelenMa's avatar
    HelenMa
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    1 year ago

    Hi Elad,

    The agilex7 transceiver IP is special for DP application.
    It can't be generated from the transceiver IP GUI, so it is not easier to modify the parameter for the transceiver.

    Please try with Arria10 or Stratix10 if your DP application is only running at 5.4GHz.


    Best Regards,
    Helen

  • Elad0708's avatar
    Elad0708
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    1 year ago

    Hi Helen,

    Just quick clarification on the process. reviewing the steps:

    1. Generate the DisplayPort using an Arria 10/Stratix 10 base.

    2. Isolate the transceiver instances from the design.

    3. Modify the configuration from 4-lanes to 8 lanes.

    4. Reintegrate the modified design into your original device using Agilex-7.

    Please let me know if it seems right.

    Best regards,

    Elad Rotem