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Elad0708's avatar
Elad0708
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2 years ago

DPX4 and DPx8 PHY

Hello, I am trying to build a PHY for DisplayPort 5.4GHz design we have. I am trying to set Dp-PHY with 4-lanes and 8-lanes, I encountered couple of issues during the process: first how can I conf...
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Elad0708's avatar
Elad0708
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2 years ago

Hi Aaron,

I need to correct my initial question. I require an 8-lane DP Tx; there's no need for RX lanes since these differential lines are directly connected to the LCD panel.

Essentially, my question pertains more to the 'gxb_tx_clkout' (link layer clock). We only need one clock for the control layer, not two from each PHY instantiation.

Regards,

Elad

  • zhenruan's avatar
    zhenruan
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    2 years ago

    Hi Elad,

    The design requires 8-lane DP Tx; You must set them into 2 interfaces. Each works at the tx-only mode and has a 4-lane DP source and a 4-channel Transceiver Native PHY TX IP. It also needs a AUX channel for the link training. That is defined in the DisplayPort protocol. The Intel DisplayPort IP just conforms the DisplayPort Standard. Please refer to the DisplayPort spec for more information.

    That also means there are two gxb_tx_clkout clocks in the design. You can't use one gxb_tx_clkout clock for the 8 channel PHY. Four channels form an HDMI interface that works together independently of the other four channels.

    Regards,

    Aaron