DPX4 and DPx8 PHY

Hey,

This is the IP listed under the generated example design folder :

dp_0_example_design/rtl/core/ip/dp_tx/dp_tx_reset_bridge.ip
dp_0_example_design/rtl/core/ip/dp_tx/dp_tx_mgmt_clk.ip
dp_0_example_design/rtl/core/ip/dp_tx/dp_tx_clk_16.ip
dp_0_example_design/rtl/core/ip/dp_tx/dp_tx_dp_source.ip
dp_0_example_design/rtl/core/ip/dp_tx/dp_tx_mgmt_bridge.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_cpu_reset_bridge.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_dp_tx_reset_bridge.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_mgmt_clk.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_dp_tx_clk_16.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_cpu.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_onchip_mem.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_jtag_uart.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_sys_clock_timer.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_sysid.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_i2c_master.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_vvp_clock_bridge.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_vvp_reset_bridge.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_vvp_tpg.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_intel_vvp_cvo_0.ip
dp_0_example_design/rtl/core/ip/dp_core/dp_core_intel_vvp_fr2cv_0.ip
dp_0_example_design/rtl/tx_phy/dp_tx_data_fifo.ip
dp_0_example_design/rtl/dp_gxb_syspll.ip
dp_0_example_design/rtl/dp_iopll.ip
dp_0_example_design/rtl/dp_pxl_iopll.ip
dp_0_example_design/rtl/reset_release.ip

I don't see any ip related to gxb_phy.. What am I missing?

Thanks,

Elad Rotem